1. Field of the Invention
The invention is generally directed to physical vapor deposition ("PVD") sputter systems. The invention is more specifically related to a multiple tier collimator system for use in PVD sputtering during the fabrication of semiconductor devices wherein it is desirable to obtain a combination of uniform deposition thickness, high deposition rate, and good step coverage.
2. Description of the Related Art
PVD sputtering is used within semiconductor processing and other arts for depositing metal films and the like onto substrate surfaces.
The substrate (e.g., a semiconductor wafer) is typically a planar disk that is positioned, face-down at the top of a vacuum plasma chamber.
A planar target is further typically positioned face-up within the chamber, in spaced apart and symmetrical counterfacing relation with the substrate. In older sputter systems the target was on top and the substrate on the bottom. The substrate-on-top versus on-bottom orientation relates to keeping the substrate surface clean and is not directly related to the present invention. For purposes of consistency, the older configuration with the substrate on the bottom will be shown, but it is to be understood that other orientations are fully within the contemplation of this invention.
The target is made of the material that is to be sputter deposited onto the substrate surface. Examples include, but are not limited to, metals such as aluminum (Al), titanium (Ti), copper (Cu) and alloys or compounds of these materials.
Fundamentally, PVD sputtering involves bombarding the surface of a target material to be deposited as the film with electrostatically accelerated argon ions. Generally, electric fields are used to accelerate ions in the plasma gas, causing them to impinge on the target surface. As a result of momentum transfer, atoms and electrons are dislodged from the target surface in an area known as the erosion region. The dislodged particles follow a generally linear trajectory from their point of emission on the target surface to a collision point on the counterfacing surface of the substrate. Physical adhesion mechanisms cause the target particles to bond to the surface of the substrate, thereby forming a film on the substrate.
The physical dimensions and positionings of the substrate and target play important roles in determining rate of deposition and the uniformity of the deposited film. The distribution of emission-inducing energy across the target also plays a role.
Ideally, the target should be very wide relative to the substrate so that the target represents an infinite source plane to the particle-receiving face of the substrate. In a such a situation, if the particle receiving face of the substrate is perfectly planar and parallel to the target, every point on the substrate receiving face will receive the same contribution of deposition particles and film thickness will be uniform across the entire substrate.
Unfortunately this ideal arrangement is not possible in practical implementations of PVD sputter chambers. The target has a finite size that is usually the same order of magnitude as that of the substrate. Non-uniformities develop across the substrate for characteristics such as deposition film thickness and deposition rate due to boundary conditions. Non-uniformities in the substrate may also result from non-uniform target erosion.
In the fabrication of semiconductor devices, the substrate surface is Often not perfectly planar. Nonlinear features such as channels and mesas are typically found on the semiconductor substrate. It is often desirable to coat the sidewalls and/or bottoms of each channel or mesa with a layer of deposition material having a prescribed thickness. However, the linear nature of the trajectories followed by the emitted target particles in PVD systems create shadow effects. Not every portion of the substrate surface receives the same amount of target material at the same rate in the case where the substrate surface includes nonlinearities such as channels or mesas.
The term, "channel" is used herein in a broad sense to include features in semiconductor devices and the like such as contact vias, trenches and other depressions which are to be fully or partially filled with deposition material. A channel 12 in wafer 10 is shown on FIGS. 1-3.
The term, "mesa" is similarly used herein in a broad sense to include any device feature rising above a surrounding plane where the feature and/or its surrounding plane are to be coated with deposition material. A mesa 14 in wafer 10 is shown on FIGS. 1-3.
The term, "step coverage" is used herein in a qualitative sense to refer to the ability to coat one or more sidewalls or bottom of a channel or mesa to a desired thickness. The term, "step coverage" is further used herein in a quantitative sense to refer to the ratio of film thickness at the bottom center or top center of a channel or mesa, respectively, relative to the general film thickness of the planar regions of the wafer.
The term, "step coverage uniformity" is used herein in a quantitative sense to mean the statistical standard deviation (sigma) of step coverage across a given substrate.
The term, "flat coverage uniformity" is used herein in a quantitative sense to mean the statistical standard deviation (sigma) of film thickness across a given substrate taking into consideration only substantially planar regions (not step regions) of the substrate surface.
The term, "bottom coverage uniformity" is used herein in a quantitative sense to mean the statistical standard deviation (sigma) of film thickness across a given substrate taking into consideration only regions at the bottom of channels or mesas.
It is desirable in PVD sputtering to control the path of the sputtered target atoms to travel substantially perpendicularly between the target and the wafer substrate. Perpendicular travel of the target atoms yields an optimal step coverage, i.e., the ratio of film thickness at the bottom or top of channel or mesa, respectively, to film thickness at the planar portions of the wafer. One conventional method of controlling the target atom path is by locating collimators within the field between the target and substrate wafer. A conventional collimator system 16 including a plurality of collimators is shown in FIG. 1 between a target 18 and a wafer 10. A collimator is preferably formed of a plurality of substantially planar surfaces of minimal thickness, which planar surfaces are provided perpendicular to the target and substrate surfaces. With such an orientation, target atoms travelling in substantially perpendicular paths will reach the substrate without contacting a collimator, but target atoms traveling along substantially oblique paths will contact the collimators and be blocked from reaching the wafer substrate.
A problem with conventional collimator systems is that, while providing good step coverage, they result in poor flat coverage uniformity across the wafer. As shown in FIGS. 2 and 3, a point P.sub.1 located directly beneath a collimator receives target atoms from a greater surface area of the target, as compared to a point P.sub.2 located between the collimators, because the point P.sub.1 is subject to less blockage, or shadowing, by the collimators than is point P.sub.2. Thus, as shown slightly exaggerated in FIG. 3 for clarity, the deposited film tends to have a greater thickness under the collimators than in areas between the collimators. Varying the dimensions of the collimators and distance between the collimator and wafer will vary the location of greatest concentration of target atoms, but areas of disproportionate concentration still occur.
If a desired minimum thickness is to be obtained at point P.sub.2, for example, an excess amount of material needs to be deposited at P.sub.1 in order to assure that the film thickness at P.sub.2 will be adequate. This is disadvantageous because it wastes target material. The target is eroded faster than absolutely necessary and has to be replaced more often. The deposition of excess target material wastes time, energy, and increases the cost of production. Moreover, in some instances, the excess material near point P.sub.1 has to be polished away or etched back in order to obtain uniform film thickness across the entire surface of the substrate. This also waste time, energy and resources.
One solution to the problem of poor flat coverage uniformity with collimators is to increase the pressure within the sputtering chamber. Increasing the pressure causes a greater number of collisions between the target atoms as they approach the wafer, and thus the atoms scatter to a greater degree. Another solution to the problem of poor flat coverage uniformity with collimators is to increase the distance between the collimators and the wafer substrate. As with increased pressure, the greater distance allows more collisions and greater scattering of the target atoms. Additionally, increasing the distance between the collimators and wafer decreases the blockage or shadow effect that the collimators provide.
However, the problem with increasing the chamber pressure and/or increasing the distance between the collimator and substrate is that these solutions increase the incidence of target atoms contacting the substrate at oblique angles, thereby resulting in poor step coverage. Thus, the prior art solutions to poor flat coverage uniformity with collimators actually negate the purpose and advantages for which collimators are intended.